A typical driving system of a flat panel display includes a timing controller, source drivers and gate drivers. The timing controller generates data, clock and synchronization signals, which are transmitted to the source drivers in a bus manner. The source drivers receive data from the timing controller according to the rising and falling edges of the clock signal. Transmission interfaces commonly used for signal transfer between the timing controller and the source drivers are interfaces with two signal levels, such as reduced swing differential signaling (RSDS) and mini low voltage differential signaling (mini-LVDS) interfaces.
As the flat panel display moves toward a large panel size, a high resolution and a high frame rate, the data transmission rate in the driving system is substantially increased. Besides, in the flat panel display, transmission of data and clock signals employs the bus transmission interface. For a large panel size of the flat panel display, the signaling lines coupling to the timing controller and different source drivers have great line length difference. Accordingly, the signaling lines corresponding to different source drivers may work under different loads, resulting in rising and falling rates of transmission signals. Additionally, since the source drivers jointly receive the data signals via a bus, the data signals received by different source drivers may have different phase delays due to different transmission line lengths. As a result, data and clock skews may occur in the transmission signals, thereby resulting in erroneous data reception in the source drivers and therefore deteriorating the performance of the flat panel display.
Therefore, a heretofore unaddressed need exists in the art to address the aforementioned deficiencies and inadequacies.